1. Field of the Invention
The invention relates to a semiconductor device, and more particularly to a semiconductor device having a chip size package (hereinafter, referred to as CSP) structure.
2. Description of the Related Art
With the recent miniaturization of information terminals such as a cellular phone and a personal digital assistance (PDA), miniaturization of semiconductor devices to be used inside, such as LSIs, has been in increasing demand. Under such circumstances, attention has been given to a packaging technology called ball grid array (BGA) structure.
Unlike conventional quad flat package (QFP) structures in which lead frames are used to connect semiconductor devices to a substrate, the BGA structure achieves substrate connection via terminals called solder bumps or solder balls which are formed on the surfaces of the semiconductor devices. According to this BGA structure, external connection terminals can be formed over the entire surfaces of semiconductor devices. This can eliminate the need for lead frames around the components, allowing a significant reduction in packaging area.
By using this BGA structure, there has been developed a packaging technology called chip size package (CSP), in which the area of a semiconductor chip and the packaging area of the same are approximately equal. There has also been developed a technology called wafer level CSP (WL-CSP), in which solder bumps are formed directly on semiconductor chips without any substrate. This promotes the miniaturization of semiconductor devices (see Japanese Patent Laid-Open Publication No. 2003-297961).
A semiconductor device to which this CSP technology is applied has external connection terminals made of solder bumps, which are often arranged systematically on the surface of the semiconductor device for the sake of connection with a printed-circuit board as shown in FIG. 1 of the above-mentioned patent document.
Meanwhile, given a semiconductor substrate having a semiconductor integrated circuit formed thereon, electrode pads intended for signal input and output are often arranged along the periphery of the semiconductor integrated circuit as is the case with the QFP structure. The electrode pads formed on the periphery of this semiconductor integrated circuit are routed by a rewiring layer to the positions of systematically-arranged solder bumps for the sake of electric connection.
Under the circumstances, the inventor has become aware of the following problem. FIG. 5 shows an example of the layout of electrode pads and solder bumps on a semiconductor device 500 having the CSP structure, showing the problem of the present invention. Electrode pads 10 are arranged along the periphery of the semiconductor device 500. Solder bumps 20, or external lead electrodes, are also arranged systematically on the semiconductor device 500. Rewiring 30 routes signals from the positions of the electrode pads 10 to the positions of the solder bumps 20, or external lead electrodes, for respective electric connections. As in FIG. 1 of the patent document, the solder bumps 20 are arranged on this semiconductor device 500 inside the electrode pads 10.
Now, focus attention on the electrode pads 10a and 10b, and the solder bumps 20a to 20d. The electrode pads 10a and 10b are connected to the inner solder bumps 20a and 20b, respectively, out of the solder bumps arranged in two rows. In this case, rewiring traces 30a and 30b must be laid so as to pass between the solder bumps 20c and 20d. 
As a result, the rewiring traces 30a and 30b have greater lengths than that of a rewiring trace 30c to be connected with the outer solder bump 20c. This causes differences in the rewiring length, which can adversely affect circuit characteristics including resistances and inductances.
In order to lower these resistances and inductances, it might be desired to put the solder bumps 20 closer to the chip edges. Nevertheless, the distance between a chip edge and a solder bump 20, designated by d in the diagram, is restricted by the rewiring. The reason is that the distances from the rewiring traces to the respective electrode pads and solder bumps must be rendered greater than a predetermined distance which is determined by design rules on the semiconductor manufacturing process of the semiconductor device 500. For example, trying to put the solder bump 20c closer to the chip edge of the semiconductor device 500 has limitations since the rewiring trace 30a and the solder bump 20c, and the rewiring trace 30a and the electrode pad 10b, must be spaced wider than a certain distance determined by the design rules.
Consequently, useless gaps required for the rewiring layout appear on the periphery of the semiconductor device 500 outside the solder bumps 20. There has thus been the problem of an increased chip size.